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Renesas Electronics /R7FA6M3AH /EDMAC0 /RMCR

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Interpret as RMCR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (0)RNR

RNR=0

Description

Receive Method Control Register

Fields

RNR

Receive Request Reset

0 (0): EDRRR.RR bit (receive request bit) is set to 0 when one frame has been received.

1 (1): EDRRR.RR bit (receive request bit) is not set to 0 when one frame has been received.

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data